Abstract
A high-performance VLSI architecture for 3-D instrumentation is proposed based on a new concurrent memory access scheme. The key concept of this architecture is to reduce the number of pixel values to be retrieved and the time required in retrieving pixel values. Accordingly, the time required for the calculation of the MAD function is reduced and operations that involve memory access are calculated in parallel by a 2-D PE array in the MADU.
| Original language | English |
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| Pages | 500-503 |
| Number of pages | 4 |
| Publication status | Published - 1996 Dec 1 |
| Event | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea Duration: 1996 Nov 18 → 1996 Nov 21 |
Other
| Other | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems |
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| City | Seoul, South Korea |
| Period | 96/11/18 → 96/11/21 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering