High resolution mapping of defects at SiO2/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy

Yuji Yamagishi; Yasuo Cho

doi:10.1109/IPFA47161.2019.8984905

High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy

Yuji Yamagishi, Yasuo Cho

New Industry Creation Hatchery Center (NICHe)

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

High resolution observation of density of interface states (Hit) at SiO₂/4H-SiC interfaces was performed by local deep level transient spectroscopy based on time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). The sizes of the non-uniform contrasts observed in the map of D_it were in the order of several tens of nanometers, which are smaller than the value reported in the previous study (>100 nm). The simulation of the tr-SNDM measurement suggested that the spatial resolution of tr-SNDM is down to the tip radius of the cantilever used for the measurement and can be smaller than the lateral spread of the depletion layer width.

Original language	English
Title of host publication	26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728135526
DOIs	https://doi.org/10.1109/IPFA47161.2019.8984905
Publication status	Published - 2019 Jul
Event	26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019 - Hangzhou, China Duration: 2019 Jul 2 → 2019 Jul 5

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019
Country/Territory	China
City	Hangzhou
Period	19/7/2 → 19/7/5

Keywords

Density of interface states
Local deep level transient spectroscopy
SiO/SiC MOS interface
Time-resolved scanning nonlinear dielectric microscopy

Access to Document

10.1109/IPFA47161.2019.8984905

Cite this

Yamagishi, Y., & Cho, Y. (2019). High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy. In 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019 Article 8984905 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA47161.2019.8984905

Yamagishi, Yuji ; Cho, Yasuo. / High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy. 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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title = "High resolution mapping of defects at SiO2/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy",

abstract = "High resolution observation of density of interface states (Hit) at SiO2/4H-SiC interfaces was performed by local deep level transient spectroscopy based on time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). The sizes of the non-uniform contrasts observed in the map of Dit were in the order of several tens of nanometers, which are smaller than the value reported in the previous study (>100 nm). The simulation of the tr-SNDM measurement suggested that the spatial resolution of tr-SNDM is down to the tip radius of the cantilever used for the measurement and can be smaller than the lateral spread of the depletion layer width.",

keywords = "Density of interface states, Local deep level transient spectroscopy, SiO/SiC MOS interface, Time-resolved scanning nonlinear dielectric microscopy",

author = "Yuji Yamagishi and Yasuo Cho",

note = "Funding Information: This work was sponsored in part by a Grant-in-Aid for Scientific Research (16H06360) from the Japan Society for the Promotion of Science.. Publisher Copyright: {\textcopyright} 2019 IEEE.; 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019 ; Conference date: 02-07-2019 Through 05-07-2019",

year = "2019",

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doi = "10.1109/IPFA47161.2019.8984905",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

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Yamagishi, Y & Cho, Y 2019, High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy. in 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019., 8984905, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Institute of Electrical and Electronics Engineers Inc., 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019, Hangzhou, China, 19/7/2. https://doi.org/10.1109/IPFA47161.2019.8984905

High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy. / Yamagishi, Yuji; Cho, Yasuo.
26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8984905 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Yamagishi Y, Cho Y. High resolution mapping of defects at SiO₂/SiC interfaces by local-DLTS based on time-resolved scanning nonlinear dielectric microscopy. In 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8984905. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA47161.2019.8984905