High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit

Tasuku Nagai; Naoya Onizawa; Takahiro Hanyu

doi:10.1109/ISMVL.2008.12

High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit

Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu

RIEC - Computing System Platforms Division

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

Original language	English
Title of host publication	Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages	70-75
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2008.12
Publication status	Published - 2008
Event	38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States Duration: 2008 May 22 → 2008 May 24

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Conference

Conference	38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Country/Territory	United States
City	Dallas, TX
Period	08/5/22 → 08/5/24

Access to Document

10.1109/ISMVL.2008.12

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Nagai, T., Onizawa, N., & Hanyu, T. (2008). High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit. In Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008 (pp. 70-75). Article 4539404 (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2008.12

@inproceedings{364664d4ca204e89a4982053bf37ee52,

title = "High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit",

abstract = "A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.",

author = "Tasuku Nagai and Naoya Onizawa and Takahiro Hanyu",

year = "2008",

doi = "10.1109/ISMVL.2008.12",

language = "English",

isbn = "9780769531557",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

pages = "70--75",

booktitle = "Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008",

note = "38th International Symposium on Multiple-Valued Logic, ISMVL 2008 ; Conference date: 22-05-2008 Through 24-05-2008",

}

Nagai, T, Onizawa, N & Hanyu, T 2008, High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit. in Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008., 4539404, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 70-75, 38th International Symposium on Multiple-Valued Logic, ISMVL 2008, Dallas, TX, United States, 08/5/22. https://doi.org/10.1109/ISMVL.2008.12

High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit. / Nagai, Tasuku; Onizawa, Naoya ; Hanyu, Takahiro.
Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008. 2008. p. 70-75 4539404 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

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High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit

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