TY - GEN
T1 - High-speed voltage-control spintronics memory (High-Speed VoCSM)
AU - Yoda, H.
AU - Sugiyama, H.
AU - Inokuchi, T.
AU - Kato, Y.
AU - Ohsawa, Y.
AU - Abe, K.
AU - Shimomura, N.
AU - Saito, Y.
AU - Shirotori, S.
AU - Koi, K.
AU - Altansargai, B.
AU - Oikawa, S.
AU - Shimizu, M.
AU - Ishikawa, M.
AU - Ikegami, K.
AU - Kamiguchi, Y.
AU - Fujita, S.
AU - Kurobe, A.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/5
Y1 - 2017/6/5
N2 - We propose a new spintronics-based memory architecture with 2 MTJs and 4 transistors as a unit cell for high-speed application. The architecture employs spin-Hall effect as a writing principle and voltage-control-magneticanisotropy (VCMA) effect as a write speed acceleration. We successfully demonstrated the unique complementary flashwriting scheme and proved a potential of ultrahigh speed writing with the prototype unit-cell and the test-element.
AB - We propose a new spintronics-based memory architecture with 2 MTJs and 4 transistors as a unit cell for high-speed application. The architecture employs spin-Hall effect as a writing principle and voltage-control-magneticanisotropy (VCMA) effect as a write speed acceleration. We successfully demonstrated the unique complementary flashwriting scheme and proved a potential of ultrahigh speed writing with the prototype unit-cell and the test-element.
UR - http://www.scopus.com/inward/record.url?scp=85023640557&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85023640557&partnerID=8YFLogxK
U2 - 10.1109/IMW.2017.7939085
DO - 10.1109/IMW.2017.7939085
M3 - Conference contribution
AN - SCOPUS:85023640557
T3 - 2017 IEEE 9th International Memory Workshop, IMW 2017
BT - 2017 IEEE 9th International Memory Workshop, IMW 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE International Memory Workshop, IMW 2017
Y2 - 14 May 2017 through 17 May 2017
ER -