High-throughput compact delay-insensitive asynchronous NoC router

Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)


A new asynchronous delay-insensitive data-transmission method based on level-encoded dual-rail (LEDR) encoding with novel packet-structure restriction is proposed to realize a high-throughput network-on-chip (NoC) router together with a compact hardware. The use of LEDR encoding makes communication steps and the registers being used half in comparison with four-phase dual-rail encoding because the spacer information of the four-phase one is eliminated, which significantly improves the network throughput. By using the proposed packet structure, the phase information of header and tail flits is uniquely determined. Since the router can be asynchronously controlled by ignoring the phase information, the circuit is compactly implemented. As a result, the proposed asynchronous NoC router on a (0.13-μ m) CMOS technology, has a 90 percent increase in throughput and a 34 percent decrease in energy dissipation with 25 percent area overhead in comparison with a conventional four-phase asynchronous NoC router under a postlayout simulation. Under a random traffic pattern in a (4 × 4) 2D mesh topology, the proposed asynchronous NoC has a 140 percent increase in throughput and half packet latency compared with the conventional one. We also fabricate the asynchronous NoC based on the proposed router on a (0.13-μ m) CMOS technology and demonstrate the chip correctly operates under a supply voltage of 0.6 to 1.8 V.

Original languageEnglish
Article number6495457
Pages (from-to)637-649
Number of pages13
JournalIEEE Transactions on Computers
Issue number3
Publication statusPublished - 2014 Mar


  • asynchronous circuits
  • level-encoded dual-rail (LEDR) encoding
  • mesh topology
  • Network-on-chip (NoC)
  • on-chip networks
  • reliability
  • spidergon topology


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