A 0.18 um generation logic technology has been developed with 0.14 um gate length transistors. Guidelines to suppress mechanical stress in Shallow Trench Isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF2 source drain ion implantation. Amorphous Si with RTA is key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in same layout rule.
|Number of pages
|Technical Digest - International Electron Devices Meeting
|Published - 1999
|1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 1999 Dec 5 → 1999 Dec 8