TY - JOUR
T1 - Highly Parallel Residue Arithmetic Chip Based on Multiple-Valued Bidirectional Current-Mode Logic
AU - Kameyama, Michitaka
AU - Higuchi, Tatsuo
AU - Sekibe, Tsutomu
PY - 1989/10
Y1 - 1989/10
N2 - This paper discusses the implementation of a residue arithmetic circuit using multiple-valued bidirectional current-mode MOS technology. Each residue digit is represented by new multiple-valued coding suitable for highly parallel computation. By the coding, mod mimultiplication can be simply performed by a shift operation. In mod addition, miradix-5 signed-digit (SD) arithmetic is employed for a high degree of parallelism and multiple-operand addition, so that high-speed arithmetic operations can be achieved. Finally, the mod7 three-operand multiply adder is designed and fabricated as an integrated circuit based on 10-μm CMOS technology.
AB - This paper discusses the implementation of a residue arithmetic circuit using multiple-valued bidirectional current-mode MOS technology. Each residue digit is represented by new multiple-valued coding suitable for highly parallel computation. By the coding, mod mimultiplication can be simply performed by a shift operation. In mod addition, miradix-5 signed-digit (SD) arithmetic is employed for a high degree of parallelism and multiple-operand addition, so that high-speed arithmetic operations can be achieved. Finally, the mod7 three-operand multiply adder is designed and fabricated as an integrated circuit based on 10-μm CMOS technology.
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U2 - 10.1109/JSSC.1989.572624
DO - 10.1109/JSSC.1989.572624
M3 - Article
AN - SCOPUS:0024755196
SN - 0018-9200
VL - 24
SP - 1404
EP - 1411
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 5
ER -