Highperformance 0.1μm gate enhancementmode inalas/ingaas hemt's using twostep recessed gate technology

Novel approach for making highperformance enhancementmode InAlAs/InGaAs HEMT's (EHEMT's) are described for the first time. Most important issue for the fabrication of EHEMT's is the suppression of the parasitic resistance due to sideetching around the gate periphery during gate recess etching. Twostep recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wetchemically down to an InP recessstopping layer and the second step removes only the recessstopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 Ωmm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1μm gate EHEMT's. This is therefore one of the promising devices for ultrahighspeed applications.