TY - JOUR
T1 - IC implementation of a switched-current chaotic neuron
AU - Herrera, Rubén
AU - Suyama, Ken
AU - Horio, Yoshihiko
AU - Aihara, Kazuyuki
PY - 1999
Y1 - 1999
N2 - A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 μm HP CMOS process. A single neuron cell occupies only 0.0076mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.
AB - A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 μm HP CMOS process. A single neuron cell occupies only 0.0076mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.
KW - Chaotic neural network
KW - Switched-current circuits
UR - http://www.scopus.com/inward/record.url?scp=0033185122&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033185122&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0033185122
SN - 0916-8508
VL - E82-A
SP - 1776
EP - 1781
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 9
ER -