Impact of floating body type DRAM with the vertical MOSFET

Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F2 and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.