Impact of Interconnections on Vertically Stacked 20 um-Thick DRAM Chips

Effect of thermo-mechanical stress (TMS) originating from CuSn micro-bumps (μ-bumps) and Cu through-Si-vias (TSVs) on the retention characteristics of 20-μm-Thick, vertically stacked dynamic random access memory (DRAM) chip has been investigated. At cumulative probability of 50 %, the retention period decreased nearly 47% for the DRAM chip having thickness value of 20 μm as compared to the retention period of 200 μm-Thick DRAM chip. Annealing at 300 °C, a compressive stress value of-200 MPa caused by Cu-TSVs was observed as the remnant stress at the periphery of the keep-out-zone, and faded quickly by moving away from the keep-out-zone. We did observe tle dependency of DRAM retention time on the TMS caused by TSVs. In the case of μ-bump, we observed a large amount of tensile stress (> +300 MPa) on the back-side of DRAM chip at right above the CuSn μ-bumps, and it led to a crack in the DRAM chip. As compared to CuSn μ-bumps, the polyimide dummy μ-bumps present in between two chip layers induced less amount of residual stress in the DRAM chip.