TY - JOUR
T1 - Impact of MTJ-based nonvolatile circuit techniques for energy-efficient binary neural network hardware
AU - Natsui, Masanori
AU - Chiba, Tomoki
AU - Hanyu, Takahiro
N1 - Publisher Copyright:
© 2020 The Japan Society of Applied Physics.
PY - 2020/5/1
Y1 - 2020/5/1
N2 - This paper describes an impact of magnetic-tunnel-junction (MTJ)-device-based nonvolatile circuit techniques and its application to energy-efficient and compact binary-neural-network hardware design. Two specific properties of the MTJ-based nonvolatile-circuit style serve as key technologies to improve energy efficiency and ensure operational reliability. The former is a nonvolatile memory function that can reduce memory-access cost by holding intermediate data close to the logic circuit in nonvolatile manner, and the latter is a variable resistance function that enables compensation for accuracy degradation due to process variation after chip fabrication. As a typical example, a circuit structure performing multiply-accumulate operation and activation function is considered. Performance evaluation based on circuit simulation shows that the circuit designed with a 40 nm MOS/MTJ-hybrid process technology can reduce energy-delay product and circuit area by 99% and 52%, respectively, compared to the conventional logic-memory-separated circuit configurations.
AB - This paper describes an impact of magnetic-tunnel-junction (MTJ)-device-based nonvolatile circuit techniques and its application to energy-efficient and compact binary-neural-network hardware design. Two specific properties of the MTJ-based nonvolatile-circuit style serve as key technologies to improve energy efficiency and ensure operational reliability. The former is a nonvolatile memory function that can reduce memory-access cost by holding intermediate data close to the logic circuit in nonvolatile manner, and the latter is a variable resistance function that enables compensation for accuracy degradation due to process variation after chip fabrication. As a typical example, a circuit structure performing multiply-accumulate operation and activation function is considered. Performance evaluation based on circuit simulation shows that the circuit designed with a 40 nm MOS/MTJ-hybrid process technology can reduce energy-delay product and circuit area by 99% and 52%, respectively, compared to the conventional logic-memory-separated circuit configurations.
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U2 - 10.35848/1347-4065/ab82ae
DO - 10.35848/1347-4065/ab82ae
M3 - Article
AN - SCOPUS:85084409275
SN - 0021-4922
VL - 59
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 5
M1 - 050602
ER -