Impact of parylene-C thickness on performance of KTaO₃ field-effect transistors with high- k oxide/parylene-C hybrid gate dielectric

The proposal of a hybrid gate dielectric systematically modulated with low-k material layer has been shown to be a promising strategy in the development of low-consumption field-effect transistors (FETs) with high performance. In this work, by fabricating KTaO₃ FETs containing Y-doped Ta₂O₅/parylene-C hybrid gate dielectrics with different ratios of component thicknesses, we explored the dependence of the transistor electrical properties on the parylene-C layer thickness. Based on the results and analysis, an optimized transistor performance was achieved with an appropriate Y-doped Ta₂O₅/parylene-C thickness ratio from the point of view on low voltage operation. This study contributes to provide guidance for future device design and applications.