TY - GEN
T1 - Impact of SiO2/Si interface micro-roughness on SILC distribution and dielectric breakdown
T2 - 2017 International Reliability Physics Symposium, IRPS 2017
AU - Park, Hyeonwoo
AU - Goto, Tetsuya
AU - Kuroda, Rihito
AU - Teramoto, Akinobu
AU - Suwa, Tomoyuki
AU - Kimoto, Daiki
AU - Sugawa, Shigetoshi
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/30
Y1 - 2017/5/30
N2 - Stress Induced Leakage Current (SILC) limits the scaling of tunnel oxide of flash memory, because it increases with the decrease of the tunnel oxide thickness. Especially, anomalously large SILC that appears on the local spots can cause bit errors. We measured Qbd and SILC characteristics of the MOSFETs with the conventional and the atomically flattened SiO2/Si interfaces, and the impact of the micro-roughness on Qbd and SILC has been investigated. It was found that both the numbers of the defects inducing Qbd and anomalous SILC are reduced by introducing the atomically flat SiO2/Si interface. And the calculated excess electric field at a projecting part is approximately 5% larger than the atomically flat part by the SILC distribution and the electric field concentration simulation. It indicates that the SiO2/Si interface micro-roughness is one of the origins that induce both the anomalous SILC and early failure in dielectric breakdown, due to localized electric field concentration effect.
AB - Stress Induced Leakage Current (SILC) limits the scaling of tunnel oxide of flash memory, because it increases with the decrease of the tunnel oxide thickness. Especially, anomalously large SILC that appears on the local spots can cause bit errors. We measured Qbd and SILC characteristics of the MOSFETs with the conventional and the atomically flattened SiO2/Si interfaces, and the impact of the micro-roughness on Qbd and SILC has been investigated. It was found that both the numbers of the defects inducing Qbd and anomalous SILC are reduced by introducing the atomically flat SiO2/Si interface. And the calculated excess electric field at a projecting part is approximately 5% larger than the atomically flat part by the SILC distribution and the electric field concentration simulation. It indicates that the SiO2/Si interface micro-roughness is one of the origins that induce both the anomalous SILC and early failure in dielectric breakdown, due to localized electric field concentration effect.
KW - Dielectric breakdown
KW - Semiconductor-insulator interface
KW - Stress induced leakage current (SILC)
KW - Surface roughness
KW - Tunnel oxide
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U2 - 10.1109/IRPS.2017.7936364
DO - 10.1109/IRPS.2017.7936364
M3 - Conference contribution
AN - SCOPUS:85024366205
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - DG7.1-DG7.5
BT - 2017 International Reliability Physics Symposium, IRPS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 2 April 2017 through 6 April 2017
ER -