Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

Tomohiro Yoshida, Kengo Kobayashi, Taiichi Otsuji, Tetsuya Suemitsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)


We report an impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs). Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different height in the stems of T-gates reveals that the parasitic gate delay decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more freedom to use the T-gate electrode with a large head in the devices for high-voltage applications.

Original languageEnglish
Title of host publicationESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
PublisherIEEE Computer Society
Number of pages4
ISBN (Print)9781479906499
Publication statusPublished - 2013
Event43rd European Solid-State Device Research Conference, ESSDERC 2013 - Bucharest, Romania
Duration: 2013 Sept 162013 Sept 20

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876


Conference43rd European Solid-State Device Research Conference, ESSDERC 2013


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