Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

Kanuku Ri; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi

doi:10.1109/IRPS.2015.7112733

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

Kanuku Ri, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300^oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300^oC for 30min. As the annealing temperature increase higher than 400^oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

Original language	English
Title of host publication	2015 IEEE International Reliability Physics Symposium, IRPS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	4C21-4C26
ISBN (Electronic)	9781467373623
DOIs	https://doi.org/10.1109/IRPS.2015.7112733
Publication status	Published - 2015 May 26
Event	IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: 2015 Apr 19 → 2015 Apr 23

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2015-May
ISSN (Print)	1541-7026

Other

Other	IEEE International Reliability Physics Symposium, IRPS 2015
Country/Territory	United States
City	Monterey
Period	15/4/19 → 15/4/23

Keywords

3-D DRAM
Capacitance-time (C-t)
Cu TSV
Cu diffusion
charge carrier lifetime
retention time

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IRPS.2015.7112733

Cite this

Ri, K., Bea, J. C., Murugesan, M., Fukushima, T., Tanaka, T., & Koyanagi, M. (2015). Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. In 2015 IEEE International Reliability Physics Symposium, IRPS 2015 (pp. 4C21-4C26). [7112733] (IEEE International Reliability Physics Symposium Proceedings; Vol. 2015-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2015.7112733

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. / Ri, Kanuku; Bea, Ji Chel; Murugesan, Mariappan et al.

2015 IEEE International Reliability Physics Symposium, IRPS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 4C21-4C26 7112733 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2015-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ri, K, Bea, JC, Murugesan, M, Fukushima, T , Tanaka, T & Koyanagi, M 2015, Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. in 2015 IEEE International Reliability Physics Symposium, IRPS 2015., 7112733, IEEE International Reliability Physics Symposium Proceedings, vol. 2015-May, Institute of Electrical and Electronics Engineers Inc., pp. 4C21-4C26, IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, United States, 15/4/19. https://doi.org/10.1109/IRPS.2015.7112733

Ri K, Bea JC, Murugesan M, Fukushima T , Tanaka T, Koyanagi M. Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. In 2015 IEEE International Reliability Physics Symposium, IRPS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 4C21-4C26. 7112733. (IEEE International Reliability Physics Symposium Proceedings). doi: 10.1109/IRPS.2015.7112733

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title = "Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM",

abstract = "Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.",

keywords = "3-D DRAM, Capacitance-time (C-t), Cu TSV, Cu diffusion, charge carrier lifetime, retention time",

author = "Kanuku Ri and Bea, {Ji Chel} and Mariappan Murugesan and Takafumi Fukushima and Tetsu Tanaka and Mitsumasa Koyanagi",

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N2 - Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

AB - Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

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Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

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