Impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip for high-reliable 3-D DRAM

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300°C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300°C annealing.