TY - GEN
T1 - Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip
AU - Lee, Kangwook
AU - Tanikawa, Seiya
AU - Naganuma, Hideki
AU - Bea, Jichel
AU - Murugesan, Mariappine
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
PY - 2014
Y1 - 2014
N2 - The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ∼ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.
AB - The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ∼ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.
KW - 3D DRAM
KW - Capacitance-time (C-t)
KW - charge carrier lifetime
KW - Cu diffusion
KW - Cu TSV
KW - retention time
UR - http://www.scopus.com/inward/record.url?scp=84905650880&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84905650880&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2014.6860634
DO - 10.1109/IRPS.2014.6860634
M3 - Conference contribution
AN - SCOPUS:84905650880
SN - 9781479933167
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - 3E.4.1-3E.4.6
BT - 2014 IEEE International Reliability Physics Symposium, IRPS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Reliability Physics Symposium, IRPS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -