Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation

Rui Liang; Sungho Lee; Yuki Miwa; Kousei Kumahara; Murugesan Mariappan; Hisashi Kino; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/3DIC48104.2019.9058843

Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation

Rui Liang, Sungho Lee, Yuki Miwa, Kousei Kumahara, Murugesan Mariappan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO₂ deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO₂liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

Original language	English
Title of host publication	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728148700
DOIs	https://doi.org/10.1109/3DIC48104.2019.9058843
Publication status	Published - 2019 Oct
Event	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan Duration: 2019 Oct 8 → 2019 Oct 10

Publication series

Name	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

Conference

Conference	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
Country/Territory	Japan
City	Sendai
Period	19/10/8 → 19/10/10

Keywords

liner dielectric
low-Temperature CVD
SiO2
TSVs

Access to Document

10.1109/3DIC48104.2019.9058843

Cite this

Liang, R., Lee, S., Miwa, Y., Kumahara, K., Mariappan, M., Kino, H., Fukushima, T., & Tanaka, T. (2019). Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation. In IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 Article 9058843 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC48104.2019.9058843

Liang, Rui ; Lee, Sungho ; Miwa, Yuki et al. / Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation. IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

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title = "Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation",

abstract = "Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD{\textregistered}. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD{\textregistered} at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD{\textregistered} has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.",

keywords = "liner dielectric, low-Temperature CVD, SiO2, TSVs",

author = "Rui Liang and Sungho Lee and Yuki Miwa and Kousei Kumahara and Murugesan Mariappan and Hisashi Kino and Takafumi Fukushima and Tetsu Tanaka",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 ; Conference date: 08-10-2019 Through 10-10-2019",

year = "2019",

month = oct,

doi = "10.1109/3DIC48104.2019.9058843",

language = "English",

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Liang, R, Lee, S, Miwa, Y, Kumahara, K, Mariappan, M, Kino, H , Fukushima, T & Tanaka, T 2019, Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation. in IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019., 9058843, IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019, Sendai, Japan, 19/10/8. https://doi.org/10.1109/3DIC48104.2019.9058843

Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation. / Liang, Rui; Lee, Sungho; Miwa, Yuki et al.
IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9058843 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Sungho

AU - Miwa, Yuki

AU - Kumahara, Kousei

AU - Mariappan, Murugesan

AU - Kino, Hisashi

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

PY - 2019/10

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N2 - Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

AB - Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

KW - liner dielectric

KW - low-Temperature CVD

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KW - TSVs

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M3 - Conference contribution

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BT - IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019

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Liang R, Lee S, Miwa Y, Kumahara K, Mariappan M, Kino H et al. Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO₂ for Low-Temperature TSV Liner Formation. In IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9058843. (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019). doi: 10.1109/3DIC48104.2019.9058843