Implementation of a large scale hardware neural network system Based on stochastic logic

Akiyoshi Momoi; Shunsuke Akimoto; Shigeo Sato; Koji Nakajima

doi:10.1109/IJCNN.2004.1381070

Implementation of a large scale hardware neural network system Based on stochastic logic

Akiyoshi Momoi, Shunsuke Akimoto, Shigeo Sato, Koji Nakajima

RIEC - Computing System Platforms Division

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

In this paper, we present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.

Original language	English
Title of host publication	2004 IEEE International Joint Conference on Neural Networks - Proceedings
Pages	2671-2675
Number of pages	5
DOIs	https://doi.org/10.1109/IJCNN.2004.1381070
Publication status	Published - 2004
Event	2004 IEEE International Joint Conference on Neural Networks - Proceedings - Budapest, Hungary Duration: 2004 Jul 25 → 2004 Jul 29

Publication series

Name	IEEE International Conference on Neural Networks - Conference Proceedings
Volume	4
ISSN (Print)	1098-7576

Conference

Conference	2004 IEEE International Joint Conference on Neural Networks - Proceedings
Country/Territory	Hungary
City	Budapest
Period	04/7/25 → 04/7/29

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10.1109/IJCNN.2004.1381070

Cite this

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title = "Implementation of a large scale hardware neural network system Based on stochastic logic",

abstract = "In this paper, we present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.",

author = "Akiyoshi Momoi and Shunsuke Akimoto and Shigeo Sato and Koji Nakajima",

year = "2004",

doi = "10.1109/IJCNN.2004.1381070",

language = "English",

isbn = "0780383591",

series = "IEEE International Conference on Neural Networks - Conference Proceedings",

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booktitle = "2004 IEEE International Joint Conference on Neural Networks - Proceedings",

note = "2004 IEEE International Joint Conference on Neural Networks - Proceedings ; Conference date: 25-07-2004 Through 29-07-2004",

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Momoi, A, Akimoto, S, Sato, S & Nakajima, K 2004, Implementation of a large scale hardware neural network system Based on stochastic logic. in 2004 IEEE International Joint Conference on Neural Networks - Proceedings. IEEE International Conference on Neural Networks - Conference Proceedings, vol. 4, pp. 2671-2675, 2004 IEEE International Joint Conference on Neural Networks - Proceedings, Budapest, Hungary, 04/7/25. https://doi.org/10.1109/IJCNN.2004.1381070

Implementation of a large scale hardware neural network system Based on stochastic logic. / Momoi, Akiyoshi; Akimoto, Shunsuke; Sato, Shigeo et al.
2004 IEEE International Joint Conference on Neural Networks - Proceedings. 2004. p. 2671-2675 (IEEE International Conference on Neural Networks - Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.

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Implementation of a large scale hardware neural network system Based on stochastic logic

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