Single-carrier (SC) transmission using frequency domain equalization (FDE) is one of the candidates for the next generation mobile communication systems expected to deliver high-speed and high-quality packet data services. Fast synchronization is critical for the performance of packet transmission systems. In this paper, a robust timing synchronization scheme for SC-FDE packet transmission is presented and its implementation is discussed. The proposed scheme uses an integration process to find the optimum timing of the guard interval (GI). An SC-FDE packet transmission system is implemented on a FPGA and its performance is analyzed through experimental data.