TY - GEN
T1 - Improved power analysis on unrolled architecture and its application to PRINCE block cipher
AU - Yli-Mäyry, Ville
AU - Homma, Naofumi
AU - Aoki, Takafumi
N1 - Funding Information:
This work has been supported by JSPS KAKENHI Grant No. 25250006. We are grateful for their support.
Publisher Copyright:
© Springer International Publishing Switzerland 2016.
PY - 2016
Y1 - 2016
N2 - This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption in a single clock cycle. Recently, low-latency block ciphers are attracting much attention due to the increasing requirement of real-time cryptosystems. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.
AB - This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption in a single clock cycle. Recently, low-latency block ciphers are attracting much attention due to the increasing requirement of real-time cryptosystems. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.
KW - Cryptographic hardware
KW - Low latency cipher
KW - Power analysis
KW - Side-channel attacks
KW - Unrolled architecture
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U2 - 10.1007/978-3-319-29078-2_9
DO - 10.1007/978-3-319-29078-2_9
M3 - Conference contribution
AN - SCOPUS:84958093738
SN - 9783319290775
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 148
EP - 163
BT - Lightweight Cryptography for Security and Privacy - 4th International Workshop, LightSec 2015, Revised Selected Papers
A2 - Güneysu, Tim
A2 - Leander, Gregor
A2 - Moradi, Amir
PB - Springer Verlag
T2 - 4th International Workshop on Lightweight Cryptography for Security and Privacy, LightSec 2015
Y2 - 10 September 2015 through 11 September 2015
ER -