Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

Kazuhiko Endo; Shin Ichi O'uchi; Yuki Ishikawa; Yongxun Liu; Takashi Matsukawa; Kunihiro Sakamoto; Meishoku Masahara; Junichi Tsukada; Kenichi Ishii; Eiichi Suzuki

doi:10.1007/978-90-481-9379-0_5

Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

Kazuhiko Endo, Shin Ichi O'uchi, Yuki Ishikawa, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Meishoku Masahara, Junichi Tsukada, Kenichi Ishii, Eiichi Suzuki

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

National Institute of Advanced Industrial Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (V_th ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.

Original language	English
Title of host publication	Emerging Technologies and Circuits
Pages	67-79
Number of pages	13
DOIs	https://doi.org/10.1007/978-90-481-9379-0_5
Publication status	Published - 2010
Event	International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Grenoble, France Duration: 2008 Jun 2 → 2008 Jun 4

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	2021 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/Territory	France
City	Grenoble
Period	08/6/2 → 08/6/4

Access to Document

10.1007/978-90-481-9379-0_5

Cite this

@inproceedings{bc4de3db7ccb43c1ad729d946502a415,

title = "Independent-double-gate FINFET SRAM cell for drastic leakage current reduction",

abstract = "The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.",

author = "Kazuhiko Endo and O'uchi, {Shin Ichi} and Yuki Ishikawa and Yongxun Liu and Takashi Matsukawa and Kunihiro Sakamoto and Meishoku Masahara and Junichi Tsukada and Kenichi Ishii and Eiichi Suzuki",

note = "Funding Information: Acknowledgement The author would like to thank Ms. Yuki Ishikawa, Dr. Yongxun Liu, Dr. Takashi Matsukawa, Dr. Shin-ichi O{\textquoteright}uch, Dr. Meishoku Masahara, Mr. Junichi Tsukada, Mr. Kenichi Ishii, Ms. Hiromi Yamauchi, and Dr. Eiichi Suzuki for their support and helpful discussions.This work was supported in part by the Innovation Research Project on Nanoelectronics Materials and Structures t from the METI.; International Conference on Integrated Circuit Design and Technology, ICICDT 2008 ; Conference date: 02-06-2008 Through 04-06-2008",

year = "2010",

doi = "10.1007/978-90-481-9379-0_5",

language = "English",

isbn = "9789048193783",

series = "Lecture Notes in Electrical Engineering",

pages = "67--79",

booktitle = "Emerging Technologies and Circuits",

}

Endo, K, O'uchi, SI, Ishikawa, Y, Liu, Y, Matsukawa, T, Sakamoto, K, Masahara, M, Tsukada, J, Ishii, K & Suzuki, E 2010, Independent-double-gate FINFET SRAM cell for drastic leakage current reduction. in Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol. 2021 LNEE, pp. 67-79, International Conference on Integrated Circuit Design and Technology, ICICDT 2008, Grenoble, France, 08/6/2. https://doi.org/10.1007/978-90-481-9379-0_5

TY - GEN

T1 - Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

AU - Endo, Kazuhiko

AU - O'uchi, Shin Ichi

AU - Ishikawa, Yuki

AU - Liu, Yongxun

AU - Matsukawa, Takashi

AU - Sakamoto, Kunihiro

AU - Masahara, Meishoku

AU - Tsukada, Junichi

AU - Ishii, Kenichi

AU - Suzuki, Eiichi

N1 - Funding Information: Acknowledgement The author would like to thank Ms. Yuki Ishikawa, Dr. Yongxun Liu, Dr. Takashi Matsukawa, Dr. Shin-ichi O’uch, Dr. Meishoku Masahara, Mr. Junichi Tsukada, Mr. Kenichi Ishii, Ms. Hiromi Yamauchi, and Dr. Eiichi Suzuki for their support and helpful discussions.This work was supported in part by the Innovation Research Project on Nanoelectronics Materials and Structures t from the METI.

PY - 2010

Y1 - 2010

N2 - The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.

AB - The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.

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U2 - 10.1007/978-90-481-9379-0_5

DO - 10.1007/978-90-481-9379-0_5

M3 - Conference contribution

AN - SCOPUS:78651527127

SN - 9789048193783

T3 - Lecture Notes in Electrical Engineering

SP - 67

EP - 79

BT - Emerging Technologies and Circuits

T2 - International Conference on Integrated Circuit Design and Technology, ICICDT 2008

Y2 - 2 June 2008 through 4 June 2008

ER -

Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

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