Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

Kazuhiko Endo, Shin Ichi O'uchi, Yuki Ishikawa, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Meishoku Masahara, Junichi Tsukada, Kenichi Ishii, Eiichi Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)


The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.

Original languageEnglish
Title of host publicationEmerging Technologies and Circuits
Number of pages13
Publication statusPublished - 2010
EventInternational Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Grenoble, France
Duration: 2008 Jun 22008 Jun 4

Publication series

NameLecture Notes in Electrical Engineering
Volume2021 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119


ConferenceInternational Conference on Integrated Circuit Design and Technology, ICICDT 2008


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