InP MISFET's with Al203/Native Oxide Double-Layer Gate Insulators

Takayuki Sawada; Shin Itagaki; Hideki Hasegawa; Hideo Ohno

doi:10.1109/T-ED.1984.21657

InP MISFET's with Al203/Native Oxide Double-Layer Gate Insulators

Takayuki Sawada, Shin Itagaki, Hideki Hasegawa, Hideo Ohno

Leadership

Hokkaido University

Research output: Contribution to journal › Article › peer-review

36 Citations (Scopus)

Abstract

Enhancement-mode InP MISFET's with anodic AI2Q3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500–3000 cm2/V. s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements, InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.

Original language	English
Pages (from-to)	1038-1043
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	31
Issue number	8
DOIs	https://doi.org/10.1109/T-ED.1984.21657
Publication status	Published - 1984 Aug

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abstract = "Enhancement-mode InP MISFET's with anodic AI2Q3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500–3000 cm2/V. s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements, InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.",

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AU - Ohno, Hideo

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N2 - Enhancement-mode InP MISFET's with anodic AI2Q3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500–3000 cm2/V. s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements, InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.

AB - Enhancement-mode InP MISFET's with anodic AI2Q3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500–3000 cm2/V. s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements, InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.

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InP MISFET's with Al203/Native Oxide Double-Layer Gate Insulators

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