Intra-chip address-presetting data-transfer scheme using four-valued encoding

Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)


This paper presents a new common-bus architecture for high-speed data transfer with transferring vast quantities of data between modules inside a VLSI chip. In the infrachip data transfer, start addresses of the source and destination modules and the number of data are sent to the target modules at the first step, which is called "address presetting". After that, only the data are transferred with the maximum width of the bus, which results in achieving high throughput of bus communication. Moreover, the use of multiple-valued data encoding together with a multiple-valued current-mode circuit technique for multi-level signal detectors makes it possible to perform higher throughput of data transfer under the bus-width constraint. In case of a 64-line bus, it is demonstrated that the peak throughput using the proposed architecture is 8 times higher than that using a binary bus architecture based on direct memory access control. Its power dissipation is reduced to about 20 percent in comparison with that of the direct memory access one under the normalized throughput in a 0.1 μm CMOS process.

Original languageEnglish
Pages (from-to)192-197
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2004
EventProceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada
Duration: 2004 May 192004 May 22


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