Investigation of local bending stress effect on complementary metal-oxide-semiconductor characteristics in thinned si chip for chip-to-wafer three-dimensional integration

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal-oxide-semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.