TY - GEN
T1 - Key technologies for 500-MHz VLSI system ultimate
AU - Tamama, Teruo
AU - Narumi, Naoaki
AU - Otsuji, Tai ichi
AU - Suzuki, Masao
AU - Sudo, Tsuneta
PY - 1988
Y1 - 1988
N2 - Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5K-gate and 400-gate ultrahigh- speed bipolar gate arrays. ULTIMATE realizes ±55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.
AB - Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5K-gate and 400-gate ultrahigh- speed bipolar gate arrays. ULTIMATE realizes ±55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.
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M3 - Conference contribution
AN - SCOPUS:0024122966
SN - 0818608706
T3 - Digest of Papers - International Test Conference
SP - 108
EP - 113
BT - Digest of Papers - International Test Conference
PB - Publ by IEEE
ER -