Local distribution of residual strain in 3-D stacked flip chips measured by strain sensor chips with 2-μm long piezoresistive gauges

Electronic products such as mobile phones and PCs have been miniaturized continuously and their functions have been improved drastically. So far, the electronic interconnection between a chip and a substrate has been wire bonding, but it has started to be changed to flip chip interconnection structures because signal delay clearly appears due to the increase of the resistance caused by the thinning of the wire. Area-arrayed tiny metallic bumps such as Cu or solder are applied to the flip chip structure and they are surrounded by insulating material (underfill) for assuring the reliability of the interconnection. Since the total thickness of the stacked structure is strictly limited for the mobile application, in particular, the thickness of a chip has been thinned to less than 50 μm to minimize the total thickness of the modules or packages. However, a distribution of local thermal strain appears clearly on the surface of the stacked silicon chip mounted using flip chip technology when the thickness of a silicon chip becomes thinner than 200 μm. This local strain distribution sometimes deteriorates the electronic performance of devices and thus, degrades their reliability. Therefore, the quantitative evaluation of the residual strain in flip chip structures has become very important. To evaluate the local stress/strain distribution quantitatively, we have successfully developed strain sensor chips with 2-μm long piezoresistive gauges that consist of diffused resistors embedded in single-crystalline silicon. The local distribution of the residual thermal strain in a silicon chip caused by the area-arrayed small bumps and the material properties of underfill material can be measured using the sensor chips. The distributions of residual strain were measured in the active layers on the stacked chip surfaces mounted by flip chip technology. The measured amplitude of the distribution of the local stress in one chip reached about 200 MPa. In addition, it was confirmed that the stress distribution in the tacked chips varied drastically depending on the bump alignment.