Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

Y. X. Liu; T. Sekigawa; T. Hayashida; T. Matsukawa; K. Endo; S. O'Uchi; K. Sakamoto; K. Ishii; T. Tsukada; Y. Ishikawa; H. Yamauchi; A. Ogura; H. Koike; E. Suzuki; M. Masahara

doi:10.1109/SOI.2008.4656344

Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

Y. X. Liu, T. Sekigawa, T. Hayashida, T. Matsukawa, K. Endo, S. O'Uchi, K. Sakamoto, K. Ishii, T. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, H. Koike, E. Suzuki, M. Masahara

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Original language	English
Title of host publication	2008 IEEE International SOI Conference Proceedings
Pages	161-162
Number of pages	2
DOIs	https://doi.org/10.1109/SOI.2008.4656344
Publication status	Published - 2008
Event	2008 IEEE International SOI Conference - New Paltz, NY, United States Duration: 2008 Oct 6 → 2008 Oct 9

Publication series

Name	Proceedings - IEEE International SOI Conference
ISSN (Print)	1078-621X

Conference

Conference	2008 IEEE International SOI Conference
Country/Territory	United States
City	New Paltz, NY
Period	08/10/6 → 08/10/9

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10.1109/SOI.2008.4656344

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Liu, Y. X., Sekigawa, T., Hayashida, T., Matsukawa, T., Endo, K., O'Uchi, S., Sakamoto, K., Ishii, K., Tsukada, T., Ishikawa, Y., Yamauchi, H., Ogura, A., Koike, H., Suzuki, E., & Masahara, M. (2008). Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. In 2008 IEEE International SOI Conference Proceedings (pp. 161-162). Article 4656344 (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2008.4656344

@inproceedings{dd6464b3686f474b90f8196341d0f64b,

title = "Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs",

author = "Liu, {Y. X.} and T. Sekigawa and T. Hayashida and T. Matsukawa and K. Endo and S. O'Uchi and K. Sakamoto and K. Ishii and T. Tsukada and Y. Ishikawa and H. Yamauchi and A. Ogura and H. Koike and E. Suzuki and M. Masahara",

year = "2008",

doi = "10.1109/SOI.2008.4656344",

language = "English",

isbn = "9781424419548",

series = "Proceedings - IEEE International SOI Conference",

pages = "161--162",

booktitle = "2008 IEEE International SOI Conference Proceedings",

note = "2008 IEEE International SOI Conference ; Conference date: 06-10-2008 Through 09-10-2008",

}

Liu, YX, Sekigawa, T, Hayashida, T, Matsukawa, T, Endo, K, O'Uchi, S, Sakamoto, K, Ishii, K, Tsukada, T, Ishikawa, Y, Yamauchi, H, Ogura, A, Koike, H, Suzuki, E & Masahara, M 2008, Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. in 2008 IEEE International SOI Conference Proceedings., 4656344, Proceedings - IEEE International SOI Conference, pp. 161-162, 2008 IEEE International SOI Conference, New Paltz, NY, United States, 08/10/6. https://doi.org/10.1109/SOI.2008.4656344

Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. / Liu, Y. X.; Sekigawa, T.; Hayashida, T. et al.
2008 IEEE International SOI Conference Proceedings. 2008. p. 161-162 4656344 (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

AU - Liu, Y. X.

AU - Sekigawa, T.

AU - Hayashida, T.

AU - Matsukawa, T.

AU - Endo, K.

AU - O'Uchi, S.

AU - Sakamoto, K.

AU - Ishii, K.

AU - Tsukada, T.

AU - Ishikawa, Y.

AU - Yamauchi, H.

AU - Ogura, A.

AU - Koike, H.

AU - Suzuki, E.

AU - Masahara, M.

PY - 2008

Y1 - 2008

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U2 - 10.1109/SOI.2008.4656344

DO - 10.1109/SOI.2008.4656344

M3 - Conference contribution

AN - SCOPUS:57749170983

SN - 9781424419548

T3 - Proceedings - IEEE International SOI Conference

SP - 161

EP - 162

BT - 2008 IEEE International SOI Conference Proceedings

T2 - 2008 IEEE International SOI Conference

Y2 - 6 October 2008 through 9 October 2008

ER -

Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

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