Logic-in-memory VLSI circuit for fully parallel nearest pattern matching based on floating-gate-MOS pass-transistor logic

A logic-in-memory VLSI circuit based on floating-gate-MOS pass-transistor logic is proposed for fully parallel nearest pattern-matching operations between a 32-bit input word and 32-bit stored reference words. The similarity between words is measured by the Manhattan distance. A 32-bit adder based on the radix-2 signed-digit number system is implemented as a floating-gate-MOS pass-transistor network, where a 32-bit reference data is stored as the threshold voltages of floating-gate MOS transistors. As a result, a fully parallel memory-data access without communication bottleneck is realized in the proposed pass-transistor network. The chip area and the power dissipation of the proposed logic-in-memory VLSI circuit are greatly reduced in comparison with those of a corresponding binary CMOS implementation while yielding almost the same switching delay.