TY - JOUR
T1 - Long-range asynchronous on-chip link based on multiple-valued single-track signaling
AU - Onizawa, Naoya
AU - Matsumoto, Atsushi
AU - Hanyu, Takahiro
PY - 2012/6
Y1 - 2012/6
N2 - We have developed a long-range asynchronous on-chip data-transmission link based on multiple-valued single-track signaling for a highly reliable asynchronous Network-on-Chip. In the proposed signaling, 1-bit data with control information is represented by using a one-digit multi-level signal, so serial data can be transmitted asynchronously using only a single wire. The small number of wires alleviates the routing complexity of wiring long-range interconnects. The use of current-mode signaling makes it possible to transmit data at high speed without buffers or repeaters over a long interconnect wire because of the low-voltage swing of signaling, and it leads to low-latency data transmission. We achieve a latency of 0.45 ns, a throughput of 1.25 Gbps, and energy dissipation of 0.58 pJ/bit with a 10-mm interconnect wire under a 0.13 μm CMOS technology. This represents an 85% decrease in latency, a 150% increase in throughput, and a 90% decrease in energy dissipation compared to a conventional serial asynchronous data-transmission link.
AB - We have developed a long-range asynchronous on-chip data-transmission link based on multiple-valued single-track signaling for a highly reliable asynchronous Network-on-Chip. In the proposed signaling, 1-bit data with control information is represented by using a one-digit multi-level signal, so serial data can be transmitted asynchronously using only a single wire. The small number of wires alleviates the routing complexity of wiring long-range interconnects. The use of current-mode signaling makes it possible to transmit data at high speed without buffers or repeaters over a long interconnect wire because of the low-voltage swing of signaling, and it leads to low-latency data transmission. We achieve a latency of 0.45 ns, a throughput of 1.25 Gbps, and energy dissipation of 0.58 pJ/bit with a 10-mm interconnect wire under a 0.13 μm CMOS technology. This represents an 85% decrease in latency, a 150% increase in throughput, and a 90% decrease in energy dissipation compared to a conventional serial asynchronous data-transmission link.
KW - Asynchronous circuits
KW - Communication link
KW - Delay-insensitive
KW - Multiple-valued current-mode (MVCM) circuits
KW - Network-on-Chip (NoC)
UR - http://www.scopus.com/inward/record.url?scp=84861833438&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84861833438&partnerID=8YFLogxK
U2 - 10.1587/transfun.E95.A.1018
DO - 10.1587/transfun.E95.A.1018
M3 - Article
AN - SCOPUS:84861833438
SN - 0916-8508
VL - E95-A
SP - 1018
EP - 1029
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 6
ER -