Low leakage current and low resistivity p⁺n diodes on Si(110) fabricated by Ga⁺ and B⁺ dual ion implantation for low temperature source-drain activation

Low leakage current and low resistivity p+n diodes on Si(110) were formed by low temperature annealing at around 550°C. Ga⁺ and B ⁺ dual (Ga⁺/B⁺) ion implantation on Si(110) followed by low temperature annealing was studied. We demonstrated that Ga ⁺/B⁺ ion implantation can make the high carrier density p⁺ layer on Si(110) at low temperature annealing. The p⁺n diodes of Ga⁺/B⁺ implanted on Si(110) followed by low temperature annealing show the ideal leakage current characteristics at room temperature. This result can apply to form the source-drain region of complementary metal-oxide-semiconductor (CMOS) devices at low temperature annealing, especially the devices fabricated on Si(110).