Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Naoya Onizawa; Warren J. Gross

doi:10.1145/2463209.2488801

Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Naoya Onizawa, Warren J. Gross

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.

Original language	English
Title of host publication	Proceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs	https://doi.org/10.1145/2463209.2488801
Publication status	Published - 2013 Jul 12
Externally published	Yes
Event	50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States Duration: 2013 May 29 → 2013 Jun 7

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	50th Annual Design Automation Conference, DAC 2013
Country/Territory	United States
City	Austin, TX
Period	13/5/29 → 13/6/7

Keywords

Associative memory
Neural network
TCAM

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

Access to Document

10.1145/2463209.2488801

Cite this

Onizawa, N & Gross, WJ 2013, Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. in Proceedings of the 50th Annual Design Automation Conference, DAC 2013., 55, Proceedings - Design Automation Conference, 50th Annual Design Automation Conference, DAC 2013, Austin, TX, United States, 13/5/29. https://doi.org/10.1145/2463209.2488801

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abstract = "We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.",

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language = "English",

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AB - We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.

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Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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