Low-power field-programmable VLSI processor using dynamic circuits

This paper proposes a low-power field-programmable VLSI processor (FPVLSI) to overcome the problem of large power consumption infield-programmable gate arrays (FPGAs). A bit-serial pipeline architecture is used in the FPVLSI to reduce the complexity of interconnection blocks. Moreover, a dual-supply-voltage scheme is effectively used to scale down the supply voltage along non-critical paths to obtain low power consumption without degrading the over-all speed performance. Its main drawback is the additional hardware cost of level converters to connect a low-supply-voltage module with a high-supply-voltage one. To solve this problem, a level-converter-less look-up table based on dynamic circuits is presented. The dynamic circuits are also useful to reduce glitch power that is one of the significant portions of the total power in FPGAs. The FPVLSI is designed based on a 0.18-μm CMOS design rule. The power consumption of the FPVLSI is reduced to 40% compared to that of the FPGA.