@inproceedings{bb310f1a32f54c469b89aa012e41d2d1,
title = "Low temperature atomically flattening of Si surface of shallow trench isolation pattern",
abstract = "Low temperature (800 °C-900 °C) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 °C-900 °C. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.",
author = "T. Goto and R. Kuroda and T. Suwa and A. Teramoto and N. Akagawa and D. Kimoto and S. Sugawa and T. Ohmi and Y. Kamata and Y. Kumagai and K. Shibusawa",
note = "Publisher Copyright: {\textcopyright} The Electrochemical Society.; Symposium on Advanced CMOS-Compatible Semiconductor Devices 17 - 227th ECS Meeting ; Conference date: 24-05-2015 Through 28-05-2015",
year = "2015",
doi = "10.1149/06605.0285ecst",
language = "English",
series = "ECS Transactions",
publisher = "Electrochemical Society Inc.",
number = "5",
pages = "285--292",
editor = "Y. Omura and Martino, {J. A.} and Raskin, {J. P.} and S. Selberherr and H. Ishii and F. Gamiz and Nguyen, {B. Y.}",
booktitle = "Advanced CMOS-Compatible Semiconductor Devices 17",
edition = "5",
}