Lowest variability SOI FinFETs having multiple Vt by back-biasing

T. Matsukawa; K. Fukuda; Y. X. Liu; K. Endo; J. Tsukada; H. Yamauchi; Y. Ishikawa; S. O'Uchi; W. Mizubayashi; S. Migita; Y. Morita; H. Ota; M. Masahara

doi:10.1109/VLSIT.2014.6894393

Lowest variability SOI FinFETs having multiple V_t by back-biasing

T. Matsukawa, K. Fukuda, Y. X. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V_t) necessary for multiple V_t solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I_on) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V_t (A_Vt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G_m). Back-biasing through the SOTB provides excellent V_t controllability keeping the low V_t variability in contrast to V_t tuning by fin channel doping.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479933310
DOIs	https://doi.org/10.1109/VLSIT.2014.6894393
Publication status	Published - 2014 Sept 8
Externally published	Yes
Event	34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States Duration: 2014 Jun 9 → 2014 Jun 12

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	34th Symposium on VLSI Technology, VLSIT 2014
Country/Territory	United States
City	Honolulu
Period	14/6/9 → 14/6/12

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2014.6894393

Cite this

Matsukawa, T., Fukuda, K., Liu, Y. X., Endo, K., Tsukada, J., Yamauchi, H., Ishikawa, Y., O'Uchi, S., Mizubayashi, W., Migita, S., Morita, Y., Ota, H., & Masahara, M. (2014). Lowest variability SOI FinFETs having multiple V_t by back-biasing. In Digest of Technical Papers - Symposium on VLSI Technology [6894393] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2014.6894393

Lowest variability SOI FinFETs having multiple V_t by back-biasing. / Matsukawa, T.; Fukuda, K.; Liu, Y. X. et al.

Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 2014. 6894393 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsukawa, T, Fukuda, K, Liu, YX, Endo, K, Tsukada, J, Yamauchi, H, Ishikawa, Y, O'Uchi, S, Mizubayashi, W, Migita, S, Morita, Y, Ota, H & Masahara, M 2014, Lowest variability SOI FinFETs having multiple V_t by back-biasing. in Digest of Technical Papers - Symposium on VLSI Technology., 6894393, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 34th Symposium on VLSI Technology, VLSIT 2014, Honolulu, United States, 14/6/9. https://doi.org/10.1109/VLSIT.2014.6894393

@inproceedings{ef9e4abe9dcc4b0a8059634a17ea1466,

title = "Lowest variability SOI FinFETs having multiple Vt by back-biasing",

abstract = "FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.",

author = "T. Matsukawa and K. Fukuda and Liu, {Y. X.} and K. Endo and J. Tsukada and H. Yamauchi and Y. Ishikawa and S. O'Uchi and W. Mizubayashi and S. Migita and Y. Morita and H. Ota and M. Masahara",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 34th Symposium on VLSI Technology, VLSIT 2014 ; Conference date: 09-06-2014 Through 12-06-2014",

year = "2014",

month = sep,

day = "8",

doi = "10.1109/VLSIT.2014.6894393",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",

}

TY - GEN

T1 - Lowest variability SOI FinFETs having multiple Vt by back-biasing

AU - Matsukawa, T.

AU - Fukuda, K.

AU - Liu, Y. X.

AU - Endo, K.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - O'Uchi, S.

AU - Mizubayashi, W.

AU - Migita, S.

AU - Morita, Y.

AU - Ota, H.

AU - Masahara, M.

PY - 2014/9/8

Y1 - 2014/9/8

N2 - FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

AB - FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

UR - http://www.scopus.com/inward/record.url?scp=84907703488&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907703488&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2014.6894393

DO - 10.1109/VLSIT.2014.6894393

M3 - Conference contribution

AN - SCOPUS:84907703488

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - Digest of Technical Papers - Symposium on VLSI Technology

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 34th Symposium on VLSI Technology, VLSIT 2014

Y2 - 9 June 2014 through 12 June 2014

ER -