Abstract
Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.
Original language | English |
---|---|
Pages (from-to) | 2386-2397 |
Number of pages | 12 |
Journal | IEICE Transactions on Information and Systems |
Volume | E91-D |
Issue number | 10 |
DOIs | |
Publication status | Published - 2008 Oct |
Keywords
- High-level synthesis
- Interconnection-aware architecture
- Stereo vision