Memory hierarchy design for jetpipeline: to execute scalar and vector instructions in parallel

Takehito Sasaki; Takuya Nakaike; Koji Takano; Masayuki Katahira; Hiroaki Kobayashi; Tadao Nakamura

Memory hierarchy design for jetpipeline: to execute scalar and vector instructions in parallel

Takehito Sasaki, Takuya Nakaike, Koji Takano, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura

INF - Computer and Mathematical Sciences

Research output: Contribution to conference › Paper › peer-review

Abstract

Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, this paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.

Original language	English
Pages	66-73
Number of pages	8
Publication status	Published - 1997 Jan 1
Event	Proceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis - Fukushima, Jpn Duration: 1997 Mar 17 → 1997 Mar 21

Other

Other	Proceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
City	Fukushima, Jpn
Period	97/3/17 → 97/3/21

ASJC Scopus subject areas

Computer Science(all)

Cite this

Memory hierarchy design for jetpipeline: to execute scalar and vector instructions in parallel. / Sasaki, Takehito; Nakaike, Takuya; Takano, Koji et al.
1997. 66-73 Paper presented at Proceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, Fukushima, Jpn.

Research output: Contribution to conference › Paper › peer-review

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AU - Katahira, Masayuki

AU - Kobayashi, Hiroaki

AU - Nakamura, Tadao

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Memory hierarchy design for jetpipeline: to execute scalar and vector instructions in parallel

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ASJC Scopus subject areas

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