MRAM cell technology for over 500-MHz SoC

Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara

Research output: Contribution to journalArticlepeer-review

44 Citations (Scopus)


This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1 mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 μm2, which is smaller than the SRAM cell area, in the 0.13-μm CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kΩ and the magnetoresistive (MR) ratio is more than 70%.

Original languageEnglish
Pages (from-to)830-838
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 2007 Apr


  • High speed
  • Low switching current
  • MRAM
  • Nonvolatile memories
  • Systems-on-chips


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