MRAM cell technology for over 500MHz SoC

N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, S. Tahara

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Citations (Scopus)


We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under Ins is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2006
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Conference2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI


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