TY - GEN
T1 - MRAM cell technology for over 500MHz SoC
AU - Sakimura, N.
AU - Sugibayashi, T.
AU - Honda, T.
AU - Honjo, H.
AU - Saito, S.
AU - Suzuki, T.
AU - Ishiwata, N.
AU - Tahara, S.
PY - 2006
Y1 - 2006
N2 - We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under Ins is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%.
AB - We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under Ins is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%.
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M3 - Conference contribution
AN - SCOPUS:39749189520
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 108
EP - 109
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -