TY - GEN
T1 - MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware
AU - Natsui, Masanori
AU - Hanyu, Takahiro
N1 - Funding Information:
Figure 2 shows a basic function of a TCU. Each value in a ternary space {-1, 0, +1} is encoded by a binary-coded ternary (BCT) representation [5] shown in Fig.2 (b). This function is represented by the truth table in Fig.2(c), which can be realized by a combination of exclusive-OR (XOR), exclusive-NOR (XNOR), and non-zero determination functions. III. TCU WITH FEEDBACK-TYPE EQUAL-RESISTANCE SENSING Figure 3 shows the circuit schematic of the proposed TCU. In this differential dynamic-logic structure, the pair of output signals (out1, out2) is determined by amplifying the voltage difference between the node A and the node B caused by the difference in MTJ device resistances on the current paths determined by input signals (in1, in2). In principle, the MTJ devices m1 and m2 have to be in a complementary state, that is, (m1, m2) equals to be either (1, 0) or (0, 1) to behave as a 1-bit memory. In contrast, the proposed circuit treats (0, 0) as one of the memory states by adding feedback loops. The feedback loop indicated by red lines senses the simultaneous voltage drop below the threshold voltage (Vth) of node A and B which caused by equal-resistance state of two MTJ devices, and stem the discharge process at the evaluation phase by controlling the gate voltage of transistors M1 to M4 as shown in Fig. 4. As a result, by assigning (1, 0), (0, 0), and (0, 1) in (in1, in2), (out1, out2), and (m1, m2) to the representations of +1, 0, and -1, and by appropriately configuring the pass transistor network, we can realize a TCU which compactly integrates the multiplication function and memory function. IV. EVALUATION We designed the proposed circuit by using a 40-nm CMOS/MTJ-hybrid process. The resistance values of the MTJ devices were set to RP = 8 [kΩ] and RAP = 16 [kΩ]. Figure 5 shows a part of the simulated waveform of this circuit. We confirmed that the proposed circuit correctly worked as a TCU for all input patterns. Table 1 summarizes the energy-delay product (EDP), circuit area, and MTJ device count of the three types of configurations: a configuration in which logic and memory functions are separately arranged, an NV-LIM configuration in previous work, and this work. The proposed circuit reduces EDP by 64.9% compared with the structure that separately arranges the multiplication function and the storage function. Moreover, thanks to the feedback-loop sensing scheme, the proposed circuit reduces circuit area by 46.5% while maintaining the almost same degree of EDP compared with our previous work. Furthermore, the proposed circuit requires only two MTJ devices to store ternary values, which reduces the power overhead related to data store operation. This result suggests that energy-efficient neural network hardware can be compactly implemented by adopting NV-LIM TCU as a basic component of quantized CNN. V. CONCLUSION In this paper, we demonstrated the effectiveness of NV-LIM gate with feedback-type equal-resistance sensing scheme through a performance evaluation of a designed TCU. As a prospect, we will consider the possibility of the further performance improvement of the proposed circuit as well as the effectiveness of NV-LIM in other components such as bitcount. ACKNOWLEDGMENT The authors thank Y. Takako of Focal Agency for excellent technical assistance. Part of this research was supported by Brainware LSI Project by MEXT, JST OPERA, and JSPS KAKENHI Grant Number 17KK0001. REFERENCES [1] M. Coubariaux, et al., NIPS, 3123 (2015). [2] F. Li and B. Liu, arXiv:1605.04711 (2016). [3] M. Natsui, et al., S3S conference (2018). [4] M. Natsui, et al., ISSCC, 202 (2019). [5] G. Frieder and C. Luk, IEEE Trans. on Computers, 23(2), 212 (1975).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10/14
Y1 - 2019/10/14
N2 - A compact and energy-efficient ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture is proposed for ternary neural network (TNN) hardware implementation. The use of feedback loops for equal-resistance sensing of magnetic tunnel junction (MTJ) devices achieves better energy efficiency as well as reduced MTJ device count and circuit area. Through an experimental evaluation of a basic component of TNN hardware, its impact on the compact and energy-efficient TNN hardware design is demonstrated.
AB - A compact and energy-efficient ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture is proposed for ternary neural network (TNN) hardware implementation. The use of feedback loops for equal-resistance sensing of magnetic tunnel junction (MTJ) devices achieves better energy efficiency as well as reduced MTJ device count and circuit area. Through an experimental evaluation of a basic component of TNN hardware, its impact on the compact and energy-efficient TNN hardware design is demonstrated.
KW - deep learning
KW - MTJ device
KW - nonvolatile logic-in-memory
KW - ternary neural network
UR - http://www.scopus.com/inward/record.url?scp=85100845670&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85100845670&partnerID=8YFLogxK
U2 - 10.1109/S3S46989.2019.9320674
DO - 10.1109/S3S46989.2019.9320674
M3 - Conference contribution
AN - SCOPUS:85100845670
T3 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
BT - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Y2 - 14 October 2019 through 17 October 2019
ER -
