MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks

Masanori Natsui; Tomoki Chiba; Takahiro Hanyu

doi:10.1109/S3S.2018.8640132

MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks

Masanori Natsui, Tomoki Chiba, Takahiro Hanyu

RIEC - Computing System Platforms Division

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

A ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture for ternary neural networks (TNNs) is proposed. The NV-LIM-based implementation achieves reduced computational cost and data transfer cost related to the inference function of deep neural networks. Through an experimental evaluation of a basic component of TNNs, its impact on the energy, delay and area overhead reduction is demonstrated.

Original language	English
Title of host publication	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676264
DOIs	https://doi.org/10.1109/S3S.2018.8640132
Publication status	Published - 2019 Feb 11
Event	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States Duration: 2018 Oct 15 → 2018 Oct 18

Publication series

Name	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Country/Territory	United States
City	Burlingame
Period	18/10/15 → 18/10/18

Keywords

Deep learning
MTJ device
Nonvolatile logic-in-memory
Ternary neural network

Access to Document

10.1109/S3S.2018.8640132

Cite this

Natsui, M., Chiba, T., & Hanyu, T. (2019). MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 Article 8640132 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640132

Natsui, Masanori ; Chiba, Tomoki ; Hanyu, Takahiro. / MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

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abstract = "A ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture for ternary neural networks (TNNs) is proposed. The NV-LIM-based implementation achieves reduced computational cost and data transfer cost related to the inference function of deep neural networks. Through an experimental evaluation of a basic component of TNNs, its impact on the energy, delay and area overhead reduction is demonstrated.",

keywords = "Deep learning, MTJ device, Nonvolatile logic-in-memory, Ternary neural network",

author = "Masanori Natsui and Tomoki Chiba and Takahiro Hanyu",

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Natsui, M, Chiba, T & Hanyu, T 2019, MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks. in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640132, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, United States, 18/10/15. https://doi.org/10.1109/S3S.2018.8640132

MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks. / Natsui, Masanori; Chiba, Tomoki; Hanyu, Takahiro.
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8640132 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Natsui, Masanori

AU - Chiba, Tomoki

AU - Hanyu, Takahiro

PY - 2019/2/11

Y1 - 2019/2/11

N2 - A ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture for ternary neural networks (TNNs) is proposed. The NV-LIM-based implementation achieves reduced computational cost and data transfer cost related to the inference function of deep neural networks. Through an experimental evaluation of a basic component of TNNs, its impact on the energy, delay and area overhead reduction is demonstrated.

AB - A ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture for ternary neural networks (TNNs) is proposed. The NV-LIM-based implementation achieves reduced computational cost and data transfer cost related to the inference function of deep neural networks. Through an experimental evaluation of a basic component of TNNs, its impact on the energy, delay and area overhead reduction is demonstrated.

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KW - MTJ device

KW - Nonvolatile logic-in-memory

KW - Ternary neural network

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M3 - Conference contribution

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BT - 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

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Natsui M, Chiba T, Hanyu T. MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8640132. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). doi: 10.1109/S3S.2018.8640132

MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks

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