TY - GEN
T1 - MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI
AU - Natsui, Masanori
AU - Hanyu, Takahiro
AU - Sakimura, Noboru
AU - Sugibayashi, Tadahiko
PY - 2013
Y1 - 2013
N2 - A cell-based design flow for MTJ/MOS-hybrid logic circuits is presented towards the realization of practical-scale logic LSI based on nonvolatile logic-in-memory architecture. Newly-developed supplementary design tools including a precise MTJ device model enable to design MTJ/MOS-hybrid logic's intellectual properties (IPs) accurately. By the use of the IPs, various pattern layouts of the MOS and MTJ/MOS-hybrid logic-circuit cells can be automatically synthesized. The effectiveness of the proposed design flow is demonstrated through typical arithmetic-circuit design examples with a nonvolatile storage capability.
AB - A cell-based design flow for MTJ/MOS-hybrid logic circuits is presented towards the realization of practical-scale logic LSI based on nonvolatile logic-in-memory architecture. Newly-developed supplementary design tools including a precise MTJ device model enable to design MTJ/MOS-hybrid logic's intellectual properties (IPs) accurately. By the use of the IPs, various pattern layouts of the MOS and MTJ/MOS-hybrid logic-circuit cells can be automatically synthesized. The effectiveness of the proposed design flow is demonstrated through typical arithmetic-circuit design examples with a nonvolatile storage capability.
UR - http://www.scopus.com/inward/record.url?scp=84883361245&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883361245&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2013.6571793
DO - 10.1109/ISCAS.2013.6571793
M3 - Conference contribution
AN - SCOPUS:84883361245
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 105
EP - 108
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -