Multiple-valued constant-power adder for cryptographic processors

Yuichi Baba, Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Citations (Scopus)


This paper presents the design of a multiple-valuedadder for tamper-resistant cryptographic processors. The proposed adder is implemented in Multiple-Valued Current- Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.

Original languageEnglish
Title of host publicationProceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Number of pages6
Publication statusPublished - 2009
Event39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan
Duration: 2009 May 212009 May 23

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X


Conference39th International Symposium on Multiple-Valued Logic, ISMVL 2009
CityNaha, Okinawa


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