TY - GEN
T1 - Multiple-valued constant-power adder for cryptographic processors
AU - Baba, Yuichi
AU - Miyamoto, Atsushi
AU - Homma, Naofumi
AU - Aoki, Takafumi
PY - 2009
Y1 - 2009
N2 - This paper presents the design of a multiple-valuedadder for tamper-resistant cryptographic processors. The proposed adder is implemented in Multiple-Valued Current- Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.
AB - This paper presents the design of a multiple-valuedadder for tamper-resistant cryptographic processors. The proposed adder is implemented in Multiple-Valued Current- Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.
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U2 - 10.1109/ISMVL.2009.9
DO - 10.1109/ISMVL.2009.9
M3 - Conference contribution
AN - SCOPUS:70349427520
SN - 9780769536071
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 239
EP - 244
BT - Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
T2 - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Y2 - 21 May 2009 through 23 May 2009
ER -