Increasing VLSI system performance requires higher bus bandwidths while maintaining low cost in area, power and complexity. Bus bandwidth improvement is historically achieved by increased clock frequency, but is restricted by a signal deterioration due to intersymbol interference (ISI). Although the use of multi-level signal can increase signaling bandwidth without increasing clock frequency. ISI becomes severer than binary signals. This paper investigates multiple-valued data recovery techniques for band-limited channels to achieve high-speed data transmission in VLSI systems. The multi-level signaling employs a simple equalization technique to improve a channel bandwidth without using a complex adaptive equalizer. Also, in order to realize band-efficient data transmission, we present intra-chip multiple-valued code-division multiple access (MV-CDMA) techniques.
|Number of pages||7|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2002|
|Event||32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States|
Duration: 2002 May 15 → 2002 May 18