Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders

Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu, Vincent C. Gaudet

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)


A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail code-word, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.

Original languageEnglish
Pages (from-to)138-143
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2005 Sept 20
Event35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada
Duration: 2005 May 192005 May 21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)


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