Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals

Nobuaki Okada; Michitaka Kameyama

doi:10.1109/ISMVL.2009.62

Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals

Nobuaki Okada, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-l multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.

Original language	English
Title of host publication	Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Pages	54-59
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2009.62
Publication status	Published - 2009 Sept 30
Event	39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan Duration: 2009 May 21 → 2009 May 23

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Country/Territory	Japan
City	Naha, Okinawa
Period	09/5/21 → 09/5/23

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

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10.1109/ISMVL.2009.62

Cite this

Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals. / Okada, Nobuaki; Kameyama, Michitaka.

Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009. 2009. p. 54-59 5010374 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okada, N & Kameyama, M 2009, Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals. in Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009., 5010374, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 54-59, 39th International Symposium on Multiple-Valued Logic, ISMVL 2009, Naha, Okinawa, Japan, 09/5/21. https://doi.org/10.1109/ISMVL.2009.62

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AB - A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-l multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.

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Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals

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