TY - GEN
T1 - Nanoscale TiN wet etching and its application for FinFET fabrication
AU - Liu, Y. X.
AU - Kamei, T.
AU - Endo, K.
AU - O'uchi, S.
AU - Tsukada, J.
AU - Yamauchi, H.
AU - Hayashida, T.
AU - Ishikawa, Y.
AU - Matsukawa, T.
AU - Sakamoto, K.
AU - Ogura, A.
AU - Masahara, M.
PY - 2009
Y1 - 2009
N2 - The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully been fabricated. These experimental results indicate that the developed nanoscale TiN wet etching technique is very useful for the tall fin CMOS fabrication.
AB - The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully been fabricated. These experimental results indicate that the developed nanoscale TiN wet etching technique is very useful for the tall fin CMOS fabrication.
UR - http://www.scopus.com/inward/record.url?scp=77949365663&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949365663&partnerID=8YFLogxK
U2 - 10.1109/ISDRS.2009.5378248
DO - 10.1109/ISDRS.2009.5378248
M3 - Conference contribution
AN - SCOPUS:77949365663
SN - 9781424460304
T3 - 2009 International Semiconductor Device Research Symposium, ISDRS '09
BT - 2009 International Semiconductor Device Research Symposium, ISDRS '09
T2 - 2009 International Semiconductor Device Research Symposium, ISDRS '09
Y2 - 9 December 2009 through 11 December 2009
ER -