New analog readout architecture for low noise CMOS image sensors using column-parallel forward noise-canceling circuitry

This paper presents a new analog readout architecture for low-noise CMOS image sensors. A proposed forward noisecanceling circuitry has been developed in our readout architecture to provide a sharper noise-filtering. The new readout architecture consists of a column high-gain amplifier with correlated-double- sampling (CDS), a column forward noisecanceling circuitry, and column sample-and-hold circuits. Through the high-gain amplifier together with the forward noise-canceling circuitry, this readout architecture effectively reduces random noise of in-pixel source follower and column amplifier as well as temporal line noise from power supplies and pulse lines. A prototype 400(H) x 250(V) CMOS image sensor using the new readout architecture has been fabricated in a 0.18 μm 1-Poly 3-Metal CMOS technology with pinned-photodiode. Both the pixel pitch and the column circuit pitch are 4.5 μm. The input-referred noise of the new readout architecture is 37 μV rms, which has been reduced by 23 % compared to that of the conventional readout architecture. The input-referred noise of the pixel with new readout architecture is 72 μV rms, which has been reduced by 24 % compared to that of the pixel with conventional readout architecture.