New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

T. Fukushima; H. Hashiguchi; J. Bea; Y. Ohara; M. Murugesan; K. W. Lee; T. Tanaka; M. Koyanagi

doi:10.1109/IEDM.2012.6479157

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

T. Fukushima, H. Hashiguchi, J. Bea, Y. Ohara, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Citations (Scopus)

Abstract

We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of < 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.

Original language	English
Title of host publication	2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages	33.3.1-33.3.4
DOIs	https://doi.org/10.1109/IEDM.2012.6479157
Publication status	Published - 2012
Event	2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States Duration: 2012 Dec 10 → 2012 Dec 13

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2012 IEEE International Electron Devices Meeting, IEDM 2012
Country/Territory	United States
City	San Francisco, CA
Period	12/12/10 → 12/12/13

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10.1109/IEDM.2012.6479157

Cite this

Fukushima, T., Hashiguchi, H., Bea, J., Ohara, Y., Murugesan, M., Lee, K. W., Tanaka, T., & Koyanagi, M. (2012). New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 (pp. 33.3.1-33.3.4). Article 6479157 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479157

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abstract = "We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of < 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.",

author = "T. Fukushima and H. Hashiguchi and J. Bea and Y. Ohara and M. Murugesan and Lee, {K. W.} and T. Tanaka and M. Koyanagi",

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doi = "10.1109/IEDM.2012.6479157",

language = "English",

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series = "Technical Digest - International Electron Devices Meeting, IEDM",

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Fukushima, T, Hashiguchi, H, Bea, J, Ohara, Y, Murugesan, M, Lee, KW, Tanaka, T & Koyanagi, M 2012, New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. in 2012 IEEE International Electron Devices Meeting, IEDM 2012., 6479157, Technical Digest - International Electron Devices Meeting, IEDM, pp. 33.3.1-33.3.4, 2012 IEEE International Electron Devices Meeting, IEDM 2012, San Francisco, CA, United States, 12/12/10. https://doi.org/10.1109/IEDM.2012.6479157

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. / Fukushima, T.; Hashiguchi, H.; Bea, J. et al.
2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 33.3.1-33.3.4 6479157 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, K. W.

AU - Tanaka, T.

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Fukushima T, Hashiguchi H, Bea J, Ohara Y, Murugesan M, Lee KW et al. New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In 2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 33.3.1-33.3.4. 6479157. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2012.6479157

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

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